Conductive lines or interconnect structures are used to connect devices in integrated circuits and to connect to external pads. A significant problem in the formation of interconnect structures is the parasitic capacitances between metal lines. Parasitic capacitances cause an increase in RC delay. In some high-speed circuits, interconnect capacitances can be the limiting factor in the speed of the integrated circuit. Thus it is desirable to reduce the interconnect capacitances. Accordingly, low dielectric constant (low-k) materials have been increasingly used. However, it has been found that low-k materials are often subject to damage during the formation of interconnect structures.
FIGS. 1 and 2 illustrate cross-sectional views in the manufacture of a typical interconnect structure. Referring to FIG. 1, an etch stop layer 12 and a low-k dielectric layer 2 are formed on a metal line 14. A photo resist 6 is formed over low-k dielectric layer 2. Photo resist 6 is then patterned as a mask. An opening 8 is formed in low-k dielectric layer 2, preferably by dry etching. Referring to FIG. 2, photo resist 6 is removed, preferably by an ashing process. Exposed etch stop layer 12 is then removed to expose underlying metal line 14. Typically, low-k dielectric layer 2 contains carbon, and the steps of etching low-k dielectric layer 2, ashing photo resist 6, and removing etch stop layer 12 generate polymers, such as CFx, as by-products. A layer of polymers is schematically illustrated as a layer 10 in FIG. 2, which covers the bottom and sidewalls of opening 8. The polymers adversely affect the characteristics and reliability of the resulting interconnect structure, thus need to be removed.
Conventionally, polymer layer 10 is removed by a wet clean process. The conventional wet clean process, however, suffers drawbacks. Referring to FIG. 3, the width of trench opening 8 is increased from a width W1 before the ashing step to a width W2 before trench opening 8 is filled. For narrow trenches having widths close to the critical dimension, the respective width change may be significant enough to affect the subsequent process steps and the characteristics of the interconnect structures.
Before the formation of a diffusion barrier layer (not shown) and the filling of trench opening 8, a pre-metal clean, which typically includes an in-situ plasma etching, is performed to remove undesired contaminations such as copper oxide. The conventional pre-metal clean process causes k value increases, micro-structure distortion and pore size enlargement, partially due to the high concentration of charges in the plasma.
Accordingly, the cleaning processes used for forming interconnect structures need to be improved.